Modules

Modules define reusable components in Verilog-A/MS. A design then consists of instances of modules connected by wires. Modules may instantiate other modules. Thus, the design is specified to the simulator by giving the name of a top-level module, which is then instantiated by the simulator. Generally the top-level module is a testbench that instantiates the device under test (DUT), and the DUT itself hierarchically instantiates all other components in the design.

Here is an example of a module definition:

module clock_gen (clk);
    parameter cycle = 20;
    output reg clk=0;

    always #(cycle/2) clk = ~clk;
endmodule

Module definitions always start with the keyword module followed by the name of the module, which is then followed by an optional pin list. The definition ends with the keyword endmodule.

It is not necessary to give a pin list, and typically top-level modules such as the testbench, do not have one:

module testbench;
    // contents ...
endmodule

The contents of modules are described in the following sections.

• Ports
• Parameters
• Declarations
  • Sized Numbers versus Arrays
  • Function Definitions
  • Task Definitions
• Continuous Assigns
• Initial and Always Processes
  • Composite Statements
  • Assignment Statements
  • Timing Statements
  • Conditional Statements
  • Looping Statements
  • Task Statements
  • Miscellaneous Statements
• Analog Processes
  • Composite Statements
  • Assignment Statements
  • Timing Statements
  • Conditional Statements
  • Looping Statements
  • Task Statements
  • Analog Initial Process
• Instantiation