# Modeling Analog to Digital Converters

The basic approach to modeling ADCs is to simply subtract an offset from the input and then scale the result such that the smallest valid input value maps to the smallest output code and the largest valid input value maps to the largest output code. Then one simply casts that value to an integer and clips the result.

Here is a Verilog-AMS model with an electrical input of a 6-bit ADC with an input range of −1 V ⋯ 1 V:

```
module adc (out, in, clk);
output [5:0] out; input in, clk;
electrical in;
integer result;
always @(posedge clk) begin
result = 64*(V(in)+1)/2;
if (result > 63) result = 63;
else if (result < 0) result = 0;
end
assign out = result;
endmodule
```

Here is the same model again, but this time with a wreal input:

```
module adc (out, in, clk);
output [5:0] out; input in, clk;
wreal in;
integer result;
always @(posedge clk) begin
result = 64*(in+1)/2;
if (result > 63) result = 63;
else if (result < 0) result = 0;
end
assign out = result;
endmodule
```

As always, things are more complex if you are limited to using Verilog-A. A similar example of an ADC model in Verilog-A is given here.