Analog Processes

An analog statement describes a continuous process, meaning that the statements are executed continuously over time. At least, that is the goal and it is worth you thinking of analog statements in this way, but in reality it is not practical to actually evaluate the statements continuously. Instead, the analog kernel will choose points in time where the analog process is evaluated so as to approximate continual evaluation. Verilog-A/MS modules have some control of which times are chosen, but it is limited. At each evaluation point the analog statement is executed completely, meaning that an analog process never blocks. For example, the analog process for a resistor might look like the following:

analog V(res) <+ r*I(res);

Analog process consist of analog procedural statements. In particular, an analog process may consist of the following statement types:

• Composite Statements
  • Sequential
• Assignment Statements
  • Contribution
  • Indirect Assignment
  • Assignment
  • Contribution versus Assignment
• Timing Statements
  • Event Statements
• Conditional Statements
  • If Statements
  • Case Statements
• Looping Statements
  • While Statements
  • For Statements
  • Repeat Statements
• Task Statements
  • System Tasks

There may be only one analog process per module.

Analog process are available in Verilog-A and Verilog-AMS.

Analog Initial Process

You can initialize your analog variables using an analog initial process:

analog initial begin
   seed = 345;
   next = 0.5/freq;
end

The terms in the expression used in an analog initial block must be constants; either number literals or parameters.