PortsΒΆ

Ports, also referred to as pins or terminals, are used when wiring the module to other modules. As such, ports are wires. Ports declarations for simple wire are wire declarations with the keyword wire replaced by one of the following direction specifiers: input, output, or inout. For example:

module inv (out, in);
   output out;
   input in;

   assign out = ~in;
endmodule

module mux (out, in0, in1, sel);
   output [7:0] out;
   input [7:0] in0, in1;
   input sel;

   assign out = sel ? in1 : in0;
endmodule

For other types of wires, or for registers (registers may only be declared as outputs), the declaration is simply preceded by the direction specifier:

module counter (out, clk);
   output reg [3:0] out;

   initial out = 0;

   always @(posedge ckl) out = out + 1;
endmodule

By default the content of multi-bit ports are interpreted as unsigned numbers (the values are interpreted as positive binary numbers). It is possible to explicitly specify whether the number is to be interpreted as a signed or unsigned number as follows:

input unsigned [3:0] gain;
input signed [6:0] offset;

In this case, gain is unsigned and offset is signed, which means it is interpreted as a twos-complement signed number. So, if gain = 4’bF, its value is interpreted as 15, and if offset = 7’b7FF, then its value is interpreted as -1.

If it is necessary to apply a discipline to a port, the port declaration should be repeated with direction specifier replaced by the discipline. For example:

module buffer (out, in);
   output out;
   input in;
   electrical out, in;

   analog V(out) <+ V(in);
endmodule

Verilog also supports buses of continuous signals and wreals (you must declare these as buses rather than arrays):

module mux (out, in, sel);
   output out;
   input [1:0] in;
   input sel;
   electrical out;
   electrical [1:0] in;

   analog begin
      @(sel)
         ;
      V(out) <+ transition(sel === 0, 0, 100n)*V(in[0]);
      V(out) <+ transition(sel === 1, 0, 100n)*V(in[1]);
   end
endmodule

module mux (out, in, sel);
   output wreal out;
   input wreal [1:0] in;
   input sel;

   assign out = sel ? in[1] : in[0];
endmodule

Note

The Cadence simulator does not seem to follow the standard when it comes to declaring buses of wreals. With the Cadence simulator you should declare buses of wreals as arrays rather than as buses:

module mux (out, in, sel);
   output wreal out;
   input wreal in[1:0];
   input sel;

   assign out = sel ? in[1] : in[0];
endmodule