The ` character (referred to as the back tick, open quote, or grave accent character) introduces a language construct used to implement compiler directives. The behavior dictated by a compiler directive takes effect as soon as the compiler reads the directive. The directive remains in effect for the rest of the compilation unless a different compiler directive specifies otherwise. A compiler directive in one file can therefore control compilation behavior in multiple description files.
Verilog-AMS generally support the following compiler directives:
`default_discipline `default_transition `define `else `endif `ifdef `ifndef `include `resetall `timescale `undef
This is only a partial list the directives that are generally available.
Defines (`define) give a name to a collection of characters. Once defined, that name can be used in lieu of the characters. The name is then referred to as a macro. Any valid identifier, including keywords already in use, can be used as a name. Once defined, the macro is referenced using its name preceded by a tick. Undefines (`undef) remove the macro.
`define size 8 electrical [0:`size-1] out;
Includes (`include) are replaced by the contents of a file. It takes the filename as an argument, which can either be specified with a relative or absolute path to the file. Included files may include other files, etc.
`ifdef, `ifndef, `else, `endif
Sections of code can be conditionally ignored using the `ifdef and `ifndef directives. It takes a macro name as an argument. With `ifdef the text that follows is ignored up to a matching `else or `endif if the argument is undefined and accepted otherwise. If `else is used, then the text between it and the matching `endif is ignored if the argument is defined, and accepted otherwise. This logic is inverted for the `ifndef directive.
Verilog-AMS supports a predefined macro to allow modules to be written that work with both IEEE 1364-1995 Verilog HDL and Verilog-AMS. The predefined macro is called __VAMS_ENABLE__.
`ifdef __VAMS_ENABLE__ parameter integer del = 1 from [1:100]; `else parameter del = 1; `endif
When the `resetall compiler directive is encountered during compilation, all compiler directives are set to their default values. This is useful for ensuring that only those directives that are desired when compiling a particular source file are active. To do so, place `resetall at the beginning of each source text file, followed immediately by the directives desired in the file.
The `timescale compiler directive defines the time unit and the time precision for the modules that follow it. The time unit and time precision is specified using either 1, 10, or 100 followed by a measurement unit of either s, ms, us, ns, ps, or fs, which represents seconds, milliseconds, microseconds, nanoseconds, picoseconds, or femptoseconds.
`timescale 10ns / 1ns
The first value given specifies the units of time used in the file and the
second specifies the precision of time. The values affect the way delays are
specified and the return value from the
$realtime function. Both are
rounded to the time precision and given in multiples of the time
unit. Thus, with the specification given in the example above, #55.79
corresponds to a delay of 558ns (55.79 × 10ns rounded to
the nearest 1 ns).
Verilog-AMS allows numbers to be specified with the SI scale factors and so with Verilog-AMS files it is generally preferable to set the time unit to be 1s and then specify the delay directly.
`timescale 1s / 1ns
Then in the example above the delay would be specified as
than 55.79, which is easier to read and less error prone.