Like variables, wires are named containers for values. They are usually stateless (meaning that they must be constantly driven or they will forget their value) and are generally used for connectivity (passing values between components).

There are two basic kinds of wires: continuous and discrete-event. Continuous wires and are available in Verilog-A and Verilog-AMS and are declared with a discipline. Discrete-event wires are available in Verilog and Verilog-AMS.


Nets are collections of wire segments that communicate signal values between components in a system. As such, they span more than one component. Nets pierce the boundary of a component through ports. Ports are declared in a module, at which point they are given a name and a direction. Thus, the names used to refer to each wire segment of a net are generally different in each of the components that the net traverses. For example, consider a slightly modified version of the D flip flop given in Overview:

`timescale 1ns/1ps

module dff(q, d, clk);
   output q;
   input clk, d;
   reg q;

   always @(posedge clk) q = d;

module dff_tb;
   wire clk;
   assign #1 clk = (clk === 0);
   initial #10 $finish();

   dff FF1(.q(out), .clk(clk), .d(out));

In this example, there are two nets, clk and out. clk is explicitly declared as a wire in dff_tb. out is not explicitly declared. Notice that clk from dff_tb also happens to be referred to as clk in FF1, however out is referred to as both q and d within FF1.


Several wires may be bundled into a bus. All buses must be declared. You can declare a bus by giving the bounds of the indices of the members of the bus. For example, the following represents one way of declaring a 16-bit bus:

wire [15:0] bus;

The bounds must be constants (derived from number literals or parameters). Unless otherwise specified, the value of a bus is treated as an unsigned number. Add the keyword signed to declare a bus whose value is treated as a signed (twos complement) number:

wire signed [15:0] offset;

An individual wire in a bus can be accessed using brackets. To get a single element from a bus, put a single index in the brackets. For example, to get the leftmost wire in bus, use bus[0]. To pull out consecutive elements of a bus to create a sub-bus give the upper and lower bounds of the desired indices and separate them with a colon. For example bus[7:4] creates a 4-bit bus by pulling out wires 7, 6, 5, and 4 from bus. If the elements are not consecutive, you can enumerate the desired indices within braces. For example, bus[{15,13,11,9,7,5,3,1}] creates a sub-bus that consists of all the members of bus that have odd indices.

Discrete-Event Wires

The values on discrete-event wires are piecewise constant, meaning that they are constant until they change, and which point the value changes abruptly (in zero time) and then is constant again until the next change.

Discrete-event wires are driven (given values) using either continuous assign statement or by connecting them to an output port of a module. For example, the following code declares a wire and implements a nand function with a continuous assign statement:

wire out;
assign out = ~(in1 && in2);

It is possible to both declare and assign a value to a wire in one statement:

wire out = ~(in1 && in2);

Several types of discrete-event wires are available.

wire, tri

wire and tri are synonymous, meaning that the two names signify the same underlying wire type. Two names are available as a way of allowing the user to describe the intent of the system. Generally use of tri is recommended if multiple drivers are expected to drive the net. In this case you are intending that each driver acts as a tri-state driver. Another way of saying this is that tri is recommended if you intend to explicitly drive a z on to the wire. Otherwise use of wire is recommended.

Conflicts on a wire or tri net result in the wire resolving to a value of x, as shown in the following table:

wire/tri 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x z

This is the default wire type. If a wire is created without it being declared, it is taken to be a wire.

wand, triand

A wand or triand wire creates a wired and connection, meaning that if driven with a 0 the wire resolves to 0 even if it is also being driven with a different value, as shown in the following table.

wand/triand 0 1 x z
0 0 0 0 0
1 0 1 x 1
x 0 x x x
z 0 1 x z

wor, trior

A wor or trior wire creates a wired or connection, meaning that if driven with a 1 the wire resolves to 1 even if it is also being driven with a different value, as shown in the following table.

wor/trior 0 1 x z
0 0 1 x 0
1 1 1 1 1
x x 1 x x
z 0 1 x z


A trireg wire remember its state when driven with a z. It acts as a simple wire if with driven by 0, 1, or x, but when driven with a z it retains the value it had before it was driven with a z.


A tri0 wire acts as a resistive pulldown, meaning that it will resolve to 0 if driven with a z.

tri0 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x 0


A tri1 wire acts as a resistive pullup, meaning that it will resolve to 1 if driven with a z.

tri1 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x 1


A supply0 wire always resolves to 0 in normal situations (it will be 0 unless driven to another value with a force statement).


A supply1 wire always resolves to 1 in normal situations (it will be 1 unless driven to another value with a force statement).


The value of wreal wires are real numbers. wreal wires are available only in Verilog-AMS.

Continuous Wires

The values on continuous wires are continuously varying, meaning that even though their values are computed by the simulator at discrete points in time, the value can be constantly changing between those points. Continuous wires represent nodes in the circuit. A node is assumed to be a infinitesimal point of interconnection. There are two physical quantities (natures) associated with nodes, the potential and the flow. Because nodes are assumed to be infinitely small, the potential everywhere on a node is assumed to be the same, and the flow enter a node always sums to zero. As such, continuous wires (nodes) satisfy Kirchhoff’s laws.

A discipline must be specified for a continuous wire if the potential or flow on a wire are accessed. The discipline controls what type of signals the wire represents, ex. electrical, mechanical, rotational, optical, thermal, etc. The most commonly used discipline is electrical. electrical is a conservative discipline, meaning that provides access to both the potential (voltage) and flow (current) of the wire. To declare an electrical wire, you would use:

wire out;
electrical out;

It is not necessary to declare simple scalar wires, so this is often shortened to:

electrical out;

Two other commonly used disciplines are voltage and current. These are both signal-flow disciplines, meaning that they provide access to one of the two signals that could be associated with a continuous wire, either the potential or the flow, but not both. Of course, voltage provides access to the potential and current to the flow. You may freely interconnect wires with electrical, voltage and current disciplines.


The reference or ground node can be accessed by using the ground statement to give it a name that can be used within a module. One may only declare a node to be ground once it has been declared to be a node with a particular discipline.


electrical gnd;
ground gnd;