Keywords

Keywords are reserved non-escaped identifiers that are used to define various language constructs. The list of reserved keywords for Verilog-AMS is shown below. Preceding a keyword with an backslash causes it to be interpreted as an escaped identifier rather than a keyword.

Keywords in Verilog-AMS

above	disable	idt	notif1	supply0
abs	discipline	idtmod	or	supply1
absdelay	driver_update	if	output	table
ac_stim	edge	ifnone	parameter	tan
acos	else	inf	pmos	tanh
acosh	end	initial	posedge	task
always	endcase	initial_step	potential	time
analog	endconnectrules	inout	pow	timer
analysis	enddiscipline	input	primitive	tran
and	endfunction	integer	pull0	tranif0
asin	endmodule	join	pull1	tranif1
asinh	endnature	laplace_nd	pulldown	transition
assign	endprimitive	laplace_np	pullup	tri
atan	endspecify	laplace_zd	rcmos	tri0
atan2	endtable	laplace_zp	real	tri1
atanh	endtask	large	realtime	triand
begin	event	last_crossing	reg	trior
branch	exclude	limexp	release	trireg
buf	exp	ln	repeat	vectored
bufif0	final_step	log	rnmos	wait
bufif1	flicker_noise	macromodule	rpmos	wand
case	flow	max	rtran	weak0
casex	for	medium	rtranif0	weak1
casez	force	min	rtranif1	while
ceil	forever	module	scalared	white_noise
cmos	fork	nand	sin	wire
connectrules	from	nature	sinh	wor
cos	function	negedge	slew	wreal
cosh	generate	net_resolution	small	xnor
cross	genvar	nmos	specify	xor
ddt	ground	noise_table	specparam	zi_nd
deassign	highz0	nor	sqrt	zi_np
default	highz1	not	strong0	zi_zd
defparam	hypot	notif0	strong1	zi_zp